EIA JESD 17:1988被替代
Latch-up In Cmos Integrated Circuits
出版：JEDEC Solid State Technology Association
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基本信息
标准编号： EIA JESD 17:1988
发布时间：1988/8/1 0:00:00
标准类别：Standard
出版单位：JEDEC Solid State Technology Association
标准页数：0
标准简介
Defines a measurement procedure for the characterization of CMOS Integrated Circuits for susceptibility and immunity to latch-up under static conditions. This test procedure is to be performed for characterization and inspection purposes only.
