
Ic Latch-Up Test
出版:JEDEC Solid State Technology Association

专家解读视频
Specifies the I-test and the overvoltage latch-up testing of integrated circuits. Establishes a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. Applies to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
Supersedes EIA JESD 17 (06/2001)